From device level all the way to block and system level, one can increase functional density and hence maintain the scaling roadmap in 3D.
In this seminar, Dr. Julien Ryckaert will evaluate the potential of exploiting the 3rd dimension to enable continuous Moore’s Law scaling. He will go through various examples of technology solutions that provide 3D scaling for Logic systems. At device level, he will review how finFET and GAA have appeared as first attempts of 3D optimization of devices. Follow-on to the first review, Dr Julien will explore how CFET and VFET can potentially further scale CMOS devices structurally. He will then look at block level scaling with Sequential 3D and functional backside wafer process.