Kelvin FONG 2017-12-05T11:11:12+00:00

Xuanyao Fong received the Ph.D. and B.Sc. degrees in electrical engineering from Purdue University, West Lafayette, IN, in 2014 and 2006, respectively.

From January to August 2007, he was an Intern Engineer with Advanced Micro Devices, Inc., Boston Design Center, Boxboro, MA. He was a Research Assistant and then Postdoctoral Research Assistant to Professor Kaushik Roy in the Nanoelectronics Research Laboratory, Purdue University, from August 2007 to May 2015. He was then a Research Scientist in the Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR) from June 2015 to November 2016. Currently, he is an Assistant Professor in the Department of Electrical & Computer Engineering at the National University of Singapore. His research interests include devices-to-systems co-design methodologies for Si and non-Si nanoelectronics; design of high performance and ultralow power logic and memory systems using spintronic devices, circuits, and architectures; and non-Boolean and analog computing paradigms using emerging technologies.

  1. X. Fong, Y. Kim, R. Venkatesan, S. H. Choday, A. Raghunathan, and K. Roy, “Spin-transfer Torque Memories: Devices, Circuits and Systems,” Proceedings of the IEEE vol. 104, iss. 7, pp. 1449-1488, Jul. 2016, doi:10.1109/JPROC.2016.2521712 [PDF]
  2. X. Fong, R. Venkatesan, D. Lee, A. Raghunathan, and K. Roy, “Embedding read-only memory in spin-transfer torque MRAM based on-chip caches,” IEEE Trans. Very Large Scale Integration (TVLSI) Systems vol. 24, no. 3, pp. 992-1002, Mar. 2016, doi:10.1109/TVLSI.2015.2439733 [PDF]
  3. X. Fong, Y. Kim, K. Yogendra, D. Fan, A. Sengupta, A. Raghunathan, and K. Roy, “Spin-transfer torque devices for logic and memory applications: prospects and perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. 35, iss. 1, pp. 1-22, Jan. 2016, doi:10.1109/TCAD.2015.2481793 Invited Paper. [PDF]
  4. X. Fong, R. Venkatesan, A. Raghunathan, and K. Roy, “Non-volatile complementary polarizer spin-transfer torque (CPSTT) on-chip caches: a device/circuit/systems perspective,” IEEE Trans. Magnetics (TMAG) vol. 50, iss. 10, art. 3400611, Oct. 2014, doi:10.1109/TMAG.2014.2326858 [PDF]
  5. X. Fong, and K. Roy, “Complementary polarizers STT-MRAM (CPSTT) for on-chip caches,” IEEE Electron Device Letters vol. 34, iss. 2, pp. 232-234, Feb. 2013, doi:10.1109/LED.2012.2234079 [PDF]
    • Errata
      1. Page 232, Title: “Complimentary” should be replaced with “Complementary”
      2. Page 232, Column 1, Last sentence of Section I: “complimentary polarizers” should be replaced with “complementary polarizers”
      3. Page 233, title in running header: “COMPLIMENTARY” should be replaced with “COMPLEMENTARY”
  6. X. Fong, Y. Kim, S. H. Choday, and K. Roy, “Failure mitigation techniques for 1T-1MTJ spin-transfer torque MRAM bit-cells,” IEEE Trans. Very Large Scale Integration (TVLSI) Systems vol. 22, iss. 2, pp. 384-395, Feb. 2014, doi:10.1109/TVLSI.2013.2239671 [PDF]
    • Errata
      1. Units of “Nominal J_{C}^{}” in Table I should be \text{``MA/cm}^{2}_{}\text{''} instead of \text{``mA/cm}^{2}_{}\text{''}
  7. X. Fong, S. H. Choday, and K. Roy, “Bit-cell level optimization for non-volatile memories using magnetic tunnel junctions and spin-transfer torque switching,” IEEE Trans. Nanotechnol. (TNANO) vol. 11, no. 1, pp. 172-181, Jan. 2012, doi:10.1109/TNANO.2011.2169456 [PDF]
  8. A. Jaiswal, X. Fong, and K. Roy, “Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies,” IEEE Journal on Emerging and Selected Topics in Circuits and Systemsvol. 6, iss. 2, pp. 120-133, Jun. 2016, doi:10.1109/JETCAS.2016.2547698 [PDF]
  9. Y. Kim, X. Fong, and K. Roy, “Spin-orbit torque based spin-dice: a true random number generator,” IEEE Magnetics Letters vol. 6, art. 3001004, Dec. 2015, doi:10.1109/LMAG.2015.2496548 [PDF]
  10. K. Kwon, X. Fong, P. Wijesinghe, P. Panda, and K. Roy, “High-Density & Robust STT-MRAM Array through Device/Circuit/Architecture Interactions,” IEEE Trans. Nanotechnol. (TNANO) vol. 14, iss. 6, pp. 1024-1034, Nov. 2015, doi:10.1109/TNANO.2015.2456510[PDF]
  11. L. Zhang, X. Fong, C.-H. Chang, Z. H. Kong, and K. Roy, “Optimizing Emerging Non-Volatile Memories for Dual-Mode Applications: Data Storage and Key Generator,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD) vol. 34, no. 7, pp. 1176-1187, Jul. 2015, doi:10.1109/TCAD.2015.2427251 [PDF]
  12. L. Zhang, X. Fong, C.-H. Chang, Z. H. Kong, and K. Roy, “Highly Reliable Spin-Transfer Torque Magnetic RAM based Physical Unclonable Function With Multi-Response-Bits Per Cell,” IEEE Trans. on Information Forensics and Security (TIFS) vol. 10, no. 8, pp. 1630-1642, Aug. 2015, doi:10.1109/TIFS.2015.2421481 [PDF]
  13. Y. Seo, X. Fong, K.-W. Kwon and K. Roy, “Spin-Hall Magnetic Random-Access Memory with Dual Read/Write Ports for On-chip Caches,” IEEE Magnetics Letters vol. 6, art. 3000204, Apr. 2015, doi:10.1109/LMAG.2015.2422260 [PDF]
  14. Y. Seo, X. Fong, and K. Roy, “Domain wall coupling based STT-MRAM for on-chip cache applications,” IEEE Trans. on Electron Devices (TED) vol. 62, iss. 2, pp. 554-560, Feb. 2015, doi:10.1109/TED.2014.2377751 [PDF]
  15. Y. Kim, X. Fong, K.-W. Kwon, M.-C. Chen, and K. Roy, “Multi-level spin-orbit torque MRAMs,” IEEE Trans. on Electron Devices (TED) vol. 62, iss. 2, pp. 561-568, Jan. 2015, doi:10.1109/TED.2014.2377721 [PDF]
  16. Z. Al Azim, X. Fong, T. Ostler, R. Chantrell, and K. Roy, “Laser induced magnetization reversal for detection in optical interconnects,” IEEE Electron Device Letters (EDL) vol. 35, iss. 12, pp. 1317-1319, Oct. 2014, doi:10.1109/LED.2014.2364232. [PDF]
  17. D. Lee, X. Fong, and K. Roy, “R-MRAM: A ROM-Embedded STT MRAM Cache,” IEEE Electron Dev. Lett. vol. 34, iss. 10, pp. 1256-1258, Oct. 2013, doi:10.1109/LED.2013.2279137 [PDF]
  18. N. N. Mojumder, X. Fong, C. Augustine, S. K. Gupta, S. H. Choday, and K. Roy, “Dual pillar spin-transfer torque MRAMs for low power applications,” ACM Journal on Emerging Technologies in Computing Systems (JETC) vol. 9, iss. 2, art. 14, May 2013, doi:10.1145/2463585.2463590 [PDF]
  19. C. Augustine, X. Fong, B. Behin-Aein, and K. Roy, “Ultra-low power nano-magnet based computing: a system-level perspective,” IEEE Trans. Nanotechnol. (TNANO) vol. 10, 4, pp. 778-788, Jul. 2010, doi:10.1109/TNANO.2010.2079941 [PDF]
  20. Y. Seo, K.-W. Kwon, X. Fong, and K. Roy, “High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM,” to appear in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, doi:10.1109/JETCAS.2016.2547701 [PDF]
  21. A. Reza, Z. Al Azim, X. Fong, and K. Roy, “Modeling and Evaluation of Topological Insulator/Ferromagnet Heterostructure Based Memory,” IEEE Trans. Electron Devices (TED) vol. 63, no. 3, pp. 1359-1367, Mar. 2016, doi:10.1109/TED.2016.2520941 [PDF]
  22. A. Sengupta, Z. Al Azim, X. Fong, and K. Roy, “Spin-orbit torque induced spike-timing dependent plasticity,” Appl. Phys. Lett. (APL), vol. 106, iss. 9, 093704, Mar. 2015, doi:10.1063/1.4914111 [PDF]
  23. K. Roy, D. Fan, X. Fong,Y. Kim, M. Sharad, S. Paul, S. Chatterjee, S. Bhunia, and S. Mukhopadhyay, “Exploring spin transfer torque devices for unconventional computing,” IEEE J. on Emerging and Selected Topics in Circuits and Systems (JETCAS) vol. 5, no. 1, pp. 5-16, Mar. 2015, doi:10.1109/JETCAS.2015.2405171Invited Paper [PDF]
  24. Y. Seo, K. Kwon, X. Fong, and K. Roy, “High Performance and Energy-Efficient On-Chip Cache using Dual Port (1R/1W) Spin-Orbit Torque MRAM,” accepted for publication in J. Emerging Topics in Cicruits and Systems (JETCAS) [PDF]
  25. C. Augustine, N. Mojumder, X. Fong, H. Choday, S. Park, and K. Roy, “Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective,” IEEE J. Sensorsvol. 12, no. 4, pp. 756-766, Apr. 2012, doi:10.1109/JSEN.2011.2124453Invited Paper[PDF]
  26. K.-W. Kwon, S. H. Choday, Y. Kim, X. Fong, S. P. Park, and K. Roy, “SHE-NVFF: spin Hall effect based nonvolatile flip flop for power gating architecture,” IEEE Electron Device Letters vol. 35, iss. 4, pp. 488-490, Apr. 2014, doi:10.1109/LED.2014.2304683 [PDF]

Dr. Fong received the AMD Design Excellence Award at Purdue in 2008, and the best paper award at the 2006 International Symposium on low power electronics and design.